1. Field of the Invention
The present invention relates generally to a data transfer system in an information processing system, such as a multi-processor system and so forth. More specifically, the invention relates to a data transfer system for transferring a set of data between a main internal memory according to a vector instruction, such as vector load, vector store and so forth, in an information processing system having the main internal memory constituted of a plurality of storage devices to be accessed by a plurality of information processing portions.
2. Description of the Related Art
Conventionally, when instructions for reading out a set of data from the main internal memory, such as a vector load instruction of a vector instruction in a multi-processor system including a main internal memory constituted of a plurality of storage devices and a plurality of information processing portions accessing the main internal memory, are issued from the information processing portions to the main internal memory without any constraint, it is possible to cause overlapping of addresses of data to be read out from the main internal memory at a certain vector length (number of element data) or element distance (an interval of element data to be loaded) designated by the vector instructions issued from respective information processing portions. In such case, a plurality of vector load instructions, issued from respective information processing portions, access the same storage device in the main internal memory and cause conflict.
Upon occurrence of conflict in accessing of the same storage device, since it is not possible to perform a read operation from the same storage device by two or more vector load instructions, a later vector load instruction cannot be executed until completion of the reading process by the preceding vector load instruction. This is one of the causes of prolongation of reading data to be transferred to the information processing portions from the storage device.
On the other hand, the read out data from the storage device, on which no conflict is caused, may return to the information processing portion at an earlier timing than the data should have been read out by the vector load instruction which is situated in waiting due to occurrence of conflict. Therefore, when the leading vector load instruction causes conflict and the trailing vector load instruction does not cause conflict, reversal of order of the read out data returned to the information processing portion from the order issuing the load command.
Therefore, in the prior art, in order to ascertain orderliness and sequentiality of the read out data, it is typical to take a measure to provide a data control device for concentrically controlling read out demand from respective information processing portions as shown in FIG. 10, or to provide an issuance control portion to enable to mutually notify the load demand issuance timing and read out completion timing between respective information processing portions and thus to control issuance of the vector load instructions so that two or more information processing portions will never access the same storage device simultaneously, as shown FIG. 11.
In FIG. 10. the vector load instructions from respective information processing portions 700a to 700n are issued to a data control portion 800 at any time as required. The data control portion 800 which received the vector load instruction includes a priority circuit for determining a priority order for the information processing portions for preferentially handling the vector load instructions according to the priority order. According to the determined priority order, the element data from memories of respective storage devices 600a to 600n of the main internal memory 500 are read out. The data control device 800 verifies that the data sequence read out from respective storage devices 600a to 600n is in correct order. Also, upon verification that all element data is obtained, the read out data is sequentially transferred to the information processing portion which issued the vector load instruction.
In the data transfer system illustrated in FIG. 10, when access to the main internal memory according to the vector load instruction from the information processing portion is initiated, access to the main internal memory according to the vector load instruction from other information processing portion will never be executed until the reading out process according to the currently executed instruction is completed.
A timing chart in FIG. 12 shows an operation when the vector load instructions are issued simultaneously to the data control portion 800 from four information processing portions A, B, C and D, as one example of operation of the system of FIG. 10. Assuming that priority order is given by the priority circuit in the data control portion 800 for reading out in the order of A, B, C, D, reading according to the vector load instruction from the information processing portion B is initiated after completion of reading according to the vector load instruction from the information processing portion A. Similarly, reading according to the vector load instruction from the information processing portion C is initiated after completion of reading according to the vector load instruction from the information processing portion B, and reading according to the vector load instruction from the information processing portion D is initiated after completion of reading according to the vector load instruction from the information processing portion C.
On the other hand, in place of the data control device 800 shown in FIG. 10, a reading out demand issuance control portion 900 is provided for each information processing portion in FIG. 11 so that the vector load instruction issuing timing and reading out completion timing are mutually notified between the information processing portions and access is controlled for avoiding simultaneous access to the main internal memory from two or more information processing portions. Each reading out demand issuance control portion 900 of each of the information processing portions 700a to 700n has a priority circuit determining the priority order for respective information processing portions for preferentially handling the vector load instructions according to the priority order. According to the determined priority order, the element data is read out from the main internal memory. At first, to all of the information processing portions 700a to 700n, vector load instruction issuance timing is notified. Each information processing portion obtaining priority right, by checking its own priority order, initiates access to the main internal memory 500. Then, a timing, at which all of the read out data is stored in each information processing portion is predicted, and the read out completion timing is notified to the respective information processing portions.
In the read out demand issuance control portion 900 in each information processing portion, subsequent reading out is managed so that subsequent reading is performed sequentially. Even in this data transfer system, similarly to the data transfer system of FIG. 10, when access to the main internal memory according to the read out demand from certain information processing portion is initiated, access to the main internal memory according to the read out demand from other information processing portions is never executed until the on-going reading out process is completed.
A timing chart of FIG. 13 shows an operation when the vector load instructions are issued simultaneously to the read out demand issuance control portion 900 from four information processing portions A, B, C and D, as one example of operation of the system of FIG. 11. At first, the read out demand issuance timing and own information processing portion number are notified from the information processing portion A to remaining, information processing portions B, C, D. Similarly, the read out demand issuance timing and own information processing portion number are notified from the information processing portion B to remaining information processing portions A, C, D, the read out demand issuance timing and own information processing portion number are notified from the information processing portion C to remaining information processing portions A, B, D, and the read out demand issuance timing and own information processing portion number are notified from the information processing portion D to remaining information processing portions A, B, C.
It is assumed that the information processing portions receiving the read out demand issuance timing perform reading in the order of A, B, C, D according to the priority order determined by the priority circuit in the read out demand issuance control portion 900. Thereafter the reading out process according to the reading out demand from the information processing portion A is initiated. At the timing of completion of reading out process, the information processing portion A issues notification to other information processing portions. The information processing portion B is responsive to the read out completion timing signal from the information processing portion A to manage issuance of the read out demand by the read out demand issuance control portion 900 so that reading out from the main internal memory is performed sequentially. Simultaneously with completion of reading out of the information processing portion A, reading out according to the read out demand from the information processing portion B is initiated. Similarly, reading out is performed sequentially in the B, C, D in order.
Such conventional data transfer system, the possibility to be kept in waiting is increased in proportion to number of the information processing portions. Also, even when the main internal memory is divided into a plurality of storage devices according to the addresses, it is still not possible to read out data from the same storage device simultaneously in parallel by a plurality of information processing portions, in practical operation. In other words, the storage device which is utilized by one information processing portion cannot be accessed by other information processing portion. Therefore, merit of the multi-processor construction cannot be completely utilized.
It should be noted that the conventional data transfer system has been disclosed in U.S. Pat. No. 4,718,006.